Variable Delayed Dual-Core Lockstep (VDCLS) Processor for Safety and Security Applications

Dual-Core Lockstep (DCLS) is one of the most commonly used techniques in applications requiring functional safety. As semiconductor process nodes keep shrinking, DCLS technique also more and frequently seen industrial or even consumer electronics. The paper presents novel approach to technique. While typical set slave core delay as a fixed number clock cycles, we allow checker run freely behind main within constrained boundaries cycles. This increases temporal diversity needed for common mode failure mitigation. system integrity provided by may be area security applications. In this paper, show that proposed Variable Delayed can flatten power consumption correlation between running cores, essential wide range attacks. was implemented RISC-V processor verified Xilinx VCU108 FPGA platform.